1. Field of the Invention
This invention relates to electronic circuitry for performing a comparison on an input signal, and in particular to a switched capacitor comparator network that performs charge sharing as an aid in making the comparison.
2. Related Art
Comparators are common electronic building blocks that find use in a wide range of applications, including analog to digital converters (ADCs). For example, in a flash ADC, a resistor string with multiple taps (or multiple single tap resistor strings), sets a unique threshold voltage at each tap. Each tap is connected to a comparator for determining whether the input voltage exceeds the threshold voltage.
Generally, two low impedance DC reference voltage sources are required to drive the start and the end of the resistor string. For high-speed comparator operation, the resistor values need to be small to reduce the settling time of kickback transients that arise when the comparators are simultaneously switched into the comparison phase. While resistive tap flash ADCs have certain advantages, they also suffer from certain drawbacks.
In particular, resistive tap ADCs require two reference voltages. Both reference voltages need to be low impedance, and, as a result, a large off-chip capacitor is generally required. The off-chip capacitor often requires the ADC chip to include extra connection pins, uses additional circuit board space, and also increases component cost. In addition, because the resistive taps draw DC current, they consume relatively large amounts of power. For high speed ADCs, where the resistor values are quite small, the power consumption is particularly high. Furthermore, some degree of cross-coupling occurs between multiple comparators through shared reference voltages.
A need exists for an improved comparator network that addresses the problems noted above and other previously experienced.
An improved comparator network is arrived at by implementing a charge sharing switched capacitor front end coupled to a comparator. The comparator network may be broadly conceptualized as a charge sharing comparator network that performs signal comparison using less power and fewer references voltages, while eliminating cross-coupling among multiple comparators, than conventional comparator network implementations.
An implementation of the comparator network includes a comparator and a switched capacitor front end coupled to the comparator. The switched capacitor front end includes an input signal sampling capacitance, a reference signal sampling capacitance, and a switch network for coupling the input signal sampling capacitance and the reference signal sampling capacitance between a sampling configuration and a charge sharing configuration.
Preferably, the input signal sampling capacitance is realized with first and second differential input sampling capacitors, and the reference signal sampling capacitance is realized with first and second differential reference signal capacitors. Clocks change the switched capacitor front end between the sampling configuration and the charge sharing configuration. The comparator network is set at a preselected voltage threshold by setting a ratio of the reference sampling capacitance to the input sampling capacitance equal to a ratio of the preselected threshold voltage to a reference voltage:
(Cref/Cin)=(Vth/Vref), or Vth=Vref*(Cref/Cin).
Thus, numerous comparator networks with individually set voltage thresholds may be cascaded to form a signal comparison network such as an ADC.
Other implementations, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.